Synopsys 2021 Hiring Freshers as R&D Engineer

Synopsys Recruitment Drive for 2021 Fresher

Synopsys 2021 Hiring Freshers as R&D Engineer at Bangalore

About Company: Synopsys technology is at the heart of innovations that are changing the way people work and play. Self-driving cars. Machines that learn. Lightning-fast communication across billions of devices in the datasphere. These breakthroughs are ushering in the era of Smart Everything―where devices are getting smarter and connected, and security is an important consideration. Powering this new era of digital innovation are high-performance silicon chips and exponentially growing amounts of software content.

Company Full Name: Synopsys

Job Title: R&D Engineer

Degree needed: BE / BTech / ME / MTech

Pass-out Year: Any Year

Location: Bangalore

Experience: 0 – 2 Years



Job Description:

Synopsys HAPS® Prototyping Solution improves time-to-market and helps avoid costly device re-spins by enabling early embedded software development and allowing hardware and software co-design well ahead of chip fabrication. Synopsys delivers ProtoCompiler and HAPS solution, which dramatically accelerate software development, hardware verification and system validation from individual IP blocks to processor subsystems to complete SoCs.

Roles and Responsibility:

  • A person in the position would be responsible for designing, developing, troubleshooting, debugging and maintaining large and efficient software systems for partitioning, logic, timing optimization,  technology mapping steps of the FPGA prototyping software.
  • The person is expected to
    • Given a requirement or functional specification, design and implement efficient data structures and algorithms in C/C++.
    • Work with AE team in test planning, execution and customer support.
    • Maintain and support existing product and features.



Requirements:

  • B.Tech/M. Tech in CS/EE from a reputed institute.
  • 0-2 years of experience in designing, developing and maintaining large EDA software.
  • Sound knowledge in data structures, graph algorithms and C/C++ programming on Windows/Unix.
  • Familiarity in digital logic design.
  • Familiarity with Verilog/VHDL RTL level designs, timing constrains, static timing analysis.
  • Working knowledge of FPGA or static timing engine is a plus.

How To Apply For This Post:

  1. All the candidates check they are eligible for this post or not.
  2. All the eligible and interested candidate Apply from link given below.

Synopsys 2021 Hiring Freshers as R&D Engineer at Bangalore




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